Recently, semiconductor device miniaturization has been driven toward smaller and smaller devices, in the sub-micron range, by means of advanced silicon fabrication technologies. As this miniaturization trend continues toward higher integration density in VLSIs and improved performance, the devices approach physical limits predicted by operating principles. For example, since reduction in device dimensions is not usually accompanied by a corresponding reduction in source-to-drain voltage, higher electric fields can be expected to be generated across the channel. Therefore, in devices with an effective channel length of 1 .mu.m or less, simply scaling down the device dimensions, without changing the supply voltage, generally results in deteriorated performance and often causes device failure. In order to overcome degraded performance, various constraints are imposed on device design.
One of the most important problems to overcome in realizing submicron VLSIs is the hot-electron effects. On the one hand, it is desirable to decrease the channel length in order to obtain faster devices and to increase packing density. On the other hand, unless reduction in device dimensions is accompanied by a corresponding reduction in the supply voltage, higher electric fields will be generated in the substrate. Such intensified electric fields cause deterioration in device reliability. Alternatively, suitable design modifications may be introduced into the device to overcome or mitigate the effect of the intensified electric field.
It is well known that one of the severest limitations imposed on the miniaturization of transistors in VLSIs is the very high electric field across the channel, which causes hot-carrier injection into the gate oxide. Under the influence of the very high electric field, carriers (electrons or holes) originating from the channel current, which gain sufficient energy, may be injected into the gate oxide in the vicinity of the drain. These trapped carriers cause device instabilities, such as threshold voltage shift and transconductance degradation.
The device illustrated in FIG. 1 represents a conventional transistor 10 wherein n+ implanted source 12 and drain 14 junction regions in semiconductor substrate 16 are self aligned with gate 18 located upon a thin gate oxide layer 20. (It should be understood that although I will be referring almost exclusively to n doped regions, p doping is also comprehended.) Absent a reduction in the supply voltage, the likelihood of the above-described hot-electron effects is increased as dimensions are reduced and the source and drain get closer.
One solution that has been successful in reducing the electric field peak has been the addition of lightly doped n- regions between the n+ regions and the channel which cause some of the channel electric field to drop therein. In recent years various device processes, such as double-diffused drain (DDD) and lightly-doped drain (LDD), have been developed to incorporate the n- regions. These have been widely studied to ascertain their effect on alleviating hot-electron effects in short channel n-type MOSFETs. It should be noted that although the nomenclature of these design techniques refers to changes in the drain region, the MOSFET devices are generally symmetrical and the similar changes are made in both the source and drain regions.
A device 22 made by the DDD fabrication method is illustrated in FIG. 2. It includes a semiconductor substrate 24 upon which are deposited a thin gate oxide 26, such as SiO.sub.2, and a conductive semiconductor gate 28, which may be made of polycrystalline silicon (polysilicon or poly). The source and drain junction regions each include a first lightly doped (n-) implant 30 of a fast diffusing material, such as phosphorus, which is self aligned with the edge of the gate 28, which serves as a mask for this purpose. The source and drain also include a second, more heavily doped (n+) implant 32 of a slower diffusing material, such as arsenic, which is also self aligned with the same edge of the gate 28. After the dopant implants have been introduced, a long (1 hour), high temperature (&gt;1000.degree. C.), drive-in is utilized to diffuse the dopant materials into the substrate and to electrically activate them. Because of their differential rates of diffusion, the faster diffusing phosphorus will be driven deeper into the substrate and also will be driven laterally further beneath the gate than the slower diffusing arsenic.
Studies of the DDD devices indicate that while they are satisfactory in some respects, i.e. they do reduce somewhat the channel electric field E.sub.max, their inherently deeper junctions, caused by the dopant being driven downwardly into the substrate, degrade the short channel effects by causing punchthrough and threshold voltage falloff of the transistor. The length (L.sub.n -) of the n- buffer region 30 between the n+ junction 32 and the channel region 34 should be accurately controlled to precisely modify the channel electric field E.sub.max. However, this is not possible with this technique because it relies upon the diffusion of atoms for locating their rest positions. Furthermore, while the electrical field may be reduced by interposition of a lightly doped region, this technique inherently requires high dopant doses in the n- region in order to allow the remote diffusion to occur.
The LDD device 36, shown in FIG. 3, was developed to overcome the disadvantages of the DDD. It includes a semiconductor substrate 38 upon which is deposited a gate oxide layer 40 and a gate 42. Lightly doped, n- source and drain junctions 44 are implanted into the substrate to be self aligned with the edges of the gate 42 which serves as a mask. Then, insulating outboard spacers 46, preferably made of SiO.sub.2 are deposited adjacent the gate to define L.sub.n -, and the heavily doped n+ source and drain junctions 48 are implanted into the substrate 38 to be self aligned with the outboard edges of the spacers 46. It can be seen that the resultant structure has certain similarities with the DDD, particularly in the location of the n- region. However, a high drive in temperature is not needed because L.sub.n - is set by the spacer width and may be accurately controlled.
Studies of the LDD devices also indicate a critical defect in this structure, attributable to the remote location of the n+ junction from the edge of the gate. This defect mechanism, known as spacer induced degradation, causes electrons to be trapped in the oxide of the n-/SiO.sub.2 spacer interface and induces a positive charge adjacent the surface of the n- at that interface. The positive charge causes a high series resistance and prevents depletion of the n- region. As a possible cure for this defect, it has been suggested to increase the dopant dose in the n- region. However, doing so would cause the n- region to be very similar to the n+ region and the channel electric field would not be lowered significantly. Another suggested cure has been the introduction of a long, high temperature drive-in step to laterally drive the n+ into closer alignment with the gate edge. Unfortunately, this will also drive the n- regions deeper and closer together, further reducing the channel length and increasing the short-channel effects.
It is the object of the present invention to provide a MOSFET design which provides self alignments for both n+ and n- source-drain implants while avoiding spacer induced degradations.
It is a further object of this invention to provide a MOSFET design which offers an excellent structure for CMOS processes in which minimum thermal processing is necessary.